The integrated circuit (IC) industry is continually striving to manufacture more robust gate dielectric materials for electrical devices. In the industry, advances in tunnel oxide formation and performance have been particularly desired. The tunnel oxide is typically the most-stressed oxide during electrical operation, and is typically a thin oxide of 90 angstroms or less in thickness. Due to its high level of stressing during operation and its thinness, the tunnel oxide needs to be made robust in order to improve integrated circuit (IC) yield and reliability. In order to improve the robustness of the tunnel oxide in a floating gate memory cell, the integrated circuit industry has exposed tunnel oxide gate dielectrics to a nitrogen-containing ambient. The nitrogen in this ambient provides nitrogen atoms which penetrate the tunnel oxide and chemically bond at the oxide-to-substrate interface whereby the tunnel oxide performance is improved.
However, the industry is continually striving to integrate more types of devices onto a single silicon substrate whereby the gate oxide optimization for one device may adversely effect another gate oxide for different device. The nitrogen exposure process which is used to form conventional tunnel oxides for floating gate structures, while enhancing the performance of tunnel oxides, will greatly degrade the stability and performance of other oxides subsequently formed in logic gate regions and high voltage regions on the same substrate.
The reason nitrogen anneals used for floating structures results in degradation of subsequently formed high voltage and low voltage gate oxides is due to the fact that the nitrogen is also incorporated into the logic and high voltage areas of the substrate as well as the tunnel oxide portions of the substrate. These nitrogen atoms, which are resident at the interface of the substrate and oxide, result in subsequent etch processing being complicated and less uniform. In addition, oxide growth from these nitrogen containing surfaces to form high voltage oxides and low voltage logic gate oxides will result in a substantially non-planar oxide surface which has increased electric fields and therefore, reduced breakdown resistance. In addition, the nitrogen atoms from the substrate may be incorporated into the bulk of subsequently-grown thermal gate oxides whereby trap sites are formed in the bulk of these oxide layers. The bulk trap sites can adversely effect leakage current between the gate and the substrate, may affect threshold voltage, and will also affect the breakdown voltage of the high voltage and logic device.
One method which can be utilized to remove impurities from a substrate before thermal oxidation is the use of a sacrificial oxide layer. A dry sacrificial oxide layer is grown on the surface of the substrate and then etched using a wet etch. The combination of the sacrificial oxidation process and the wet etching reduces impurities at the surface of the substrate where subsequent thermal oxidation is to occur. However, sacrificial oxides add an additional growth step and etch step to the process. Sacrificial oxides may increase the thermal budget of the overall process, and may not be able to remove all of the nitrogen contamination from the substrate whereby the planarity of the thermally grown oxide is affected and breakdown voltage is reduced. In addition, too many sacrificial oxide processes in one process flow will thin field oxide isolation regions or trench fill material whereby device-to-device isolation across the integrated circuit (IC) is adversely affected. Therefore, the use of dry sacrificial oxides alone is not comprehensive enough to completely remove all of the nitrogen-doping problems associated with highly integrated products which utilize floating gates with nitrogen doped tunnel oxides.
A process known as wet oxidation has been used in the art for the formation of logic gate structures. Wet oxidation, however, is viewed as disadvantageous since wet oxidation provides a faster growth rate, which tends to be harder to control, than dry oxidation which has become the industry standard for gate oxidation. In addition, wet oxidation may increase the number of traps in the oxide layer. There is currently no known data showing that any wet oxidation would improve the breakdown voltage of high voltage oxides grown in areas which have previously been exposed to nitrogen atoms. There is further no known literature stating that high voltage products can be manufactured using wet oxidation whereby nitrogen-exposed tunnel oxides can also be integrated with these high voltage devices at a high performance level.
Therefore, there is a need in the IC industry for a new gate oxidation process which can be easily integrated to form ICs containing one or more of logic devices and/or high voltage devices along with floating gate arrays. In addition, this new gate oxide process should have a reduced thermal budget, improved or maintained transistor breakdown voltage operation, and improved charge-to-breakdown (Qbd), whereby gate oxide planarity is improved (reducing electric field strength across gate oxide) and nitrogen doping in the bulk of the oxide is also reduced. Furthermore, this new oxidation process should be capable of being utilized without sacrificial oxide processing, whereby field oxide isolation is not adversely eroded.